Generation of Sequential Symbolic Network Functions for Large-Scale Networks by Circuit Reductions to a Two-Port

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dc.contributor.author Pierzchala Marian en_US
dc.contributor.author Rodanski Benedykt en_US
dc.date.accessioned 2009-12-21T03:53:02Z
dc.date.available 2009-12-21T03:53:02Z
dc.date.issued 2001 en_US
dc.identifier 2004004455 en_US
dc.identifier.citation Pierzchala Marian and Rodanski Benedykt 2001, 'Generation of Sequential Symbolic Network Functions for Large-Scale Networks by Circuit Reductions to a Two-Port', IEEE, vol. 48, no. 7, pp. 906-909. en_US
dc.identifier.issn 1057-7122 en_US
dc.identifier.other C1 en_US
dc.identifier.uri http://hdl.handle.net/10453/5835
dc.description.abstract The major stumbling block in symbolic analysis of large-scale circuits is the exponential growth of expression complexity with the circuit size. Sequential techniques, introduced more than a decade ago, reduced that growth to quasi-linear. The fundamental assumption in all sequential methods developed so far was that the circuit must be decomposed in order to reduce the complexity of the final expression. In this paper we will show conclusively that this is not the case.We describe a new algebraic approach to symbolic analysis of large-scale networks, based on the reduction of the compacted modified node admittance matrix to a two-port matrix. No circuit partitioning is required. Internal variables are suppressed one by one using Gaussian elimination. To minimize the number of symbolic operations we employ a locally optimal pivoting strategy. Formula complexity is estimated to grow quasi-linearly with circuit size. The technique is conceptually very simple and produces sequential formulae of significantly lesser complexity than any exact method published to date. en_US
dc.publisher Institute of Electrical and Electronics Engineers en_US
dc.relation.isbasedon http://dx.doi.org/10.1109/81.933334 en_US
dc.title Generation of Sequential Symbolic Network Functions for Large-Scale Networks by Circuit Reductions to a Two-Port en_US
dc.parent IEEE Trans. On Circuits and Systems -I: Fundamental Theory and Applications en_US
dc.journal.volume 48 en_US
dc.journal.number 7 en_US
dc.publocation Piscataway, USA en_US
dc.identifier.startpage 906 en_US
dc.identifier.endpage 909 en_US
dc.cauo.name Engineering en_US


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