| dc.contributor.author | Sithamparanathan Kandeepan | en_US |
| dc.contributor.author | Reisenfeld Sam | en_US |
| dc.contributor.editor | Judy ?? | en_US |
| dc.date.accessioned | 2009-11-09T05:37:56Z | |
| dc.date.available | 2009-11-09T05:37:56Z | |
| dc.date.issued | 2004 | en_US |
| dc.identifier | 2004002034 | en_US |
| dc.identifier.citation | Sithamparanathan Kandeepan and Reisenfeld Sam 2004, 'Acquisition Performance of a Digital Phase Locked Loop with a Four-Quadrant Arctan Phase Detector', ISPACS Committee, Seoul, Korea, pp. 1-5. | en_US |
| dc.identifier.issn | 0-7803-8640-X | en_US |
| dc.identifier.other | E1 | en_US |
| dc.identifier.uri | http://hdl.handle.net/10453/3028 | |
| dc.description.abstract | The acquisition performance of a digital phase locked loop (DPLL) with a four-quadrant arctan based phase detector (PD) is discussed in this paper. In the noiseless case, unlike the traditional sine function based phase locked loops, the acquisition process of the four-quadrant arctan based phase locked loops is less tedious. We will look into the pull-in process together with a time-series analysis of the DPLL for the noiseless case. The phaseplane portrait of loop is also discussed, for both the noiseless and the noisy conditions. | en_US |
| dc.publisher | ISPACS Committee | en_US |
| dc.relation.isbasedon | http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=1439139&isnumber=30963 | en_US |
| dc.title | Acquisition Performance of a Digital Phase Locked Loop with a Four-Quadrant Arctan Phase Detector | en_US |
| dc.parent | Proceedings of 2004 International Symposium on Intelligent Signal Processing and Communication Systems, 2004. ISPACS 2004 | en_US |
| dc.journal.volume | en_US | |
| dc.journal.number | en_US | |
| dc.publocation | Seoul, Korea | en_US |
| dc.identifier.startpage | 1 | en_US |
| dc.identifier.endpage | 5 | en_US |
| dc.cauo.name | Engineering | en_US |
| dc.conference | ISPACS | en_US |
| dc.conference.location | Seoul, Korea | en_US |