Design of MIMO Testbed with an FPGA Board for Fast Signal Processing

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dc.contributor.author Postula, Adam. en_AU
dc.contributor.author Bialkowski, Marek E. en_AU
dc.contributor.author Bialkowski, Konstanty S. en_AU
dc.contributor.author Uthansakul, Peerapong. en_AU
dc.date.accessioned 2007-03-12T22:05:33Z
dc.date.accessioned 2012-12-15T02:29:41Z
dc.date.available 2007-03-12T22:05:33Z
dc.date.available 2012-12-15T02:29:41Z
dc.date.issued 2007-03-12T22:05:33Z
dc.identifier.uri http://hdl.handle.net/2100/86
dc.identifier.uri http://hdl.handle.net/10453/19648
dc.description.abstract This paper describes the design of a Multiple Input Multiple Output testbed for assessing various MIMO transmission schemes in rich scattering indoor environments. In the undertaken design, a Field Programmable Gate Array (FPGA) board is used for fast processing of Intermediate Frequency signals. At the present stage, the testbed performance is assessed when the channel emulator between transmitter and receiver modules is introduced. Here, the results are presented for the case when a 2x2 Alamouti scheme for space time coding/decoding at transmitter and receiver is used. Various programming details of the FPGA board along with the obtained simulation results are reported en_AU
dc.format.extent 424395 bytes
dc.format.mimetype application/pdf
dc.language.iso en_AU
dc.title Design of MIMO Testbed with an FPGA Board for Fast Signal Processing en_AU


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