A Software Phase-Locked Loop from Theory to Practice: TMS320C6000 DSP Based Implementation and Analysis

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dc.contributor.author Sithamparanathan Kandeepan en_AU
dc.date.accessioned 2007-03-12T22:05:36Z
dc.date.accessioned 2012-12-15T02:29:32Z
dc.date.available 2007-03-12T22:05:36Z
dc.date.available 2012-12-15T02:29:32Z
dc.date.issued 2007-03-12T22:05:36Z
dc.identifier.uri http://hdl.handle.net/2100/100
dc.identifier.uri http://hdl.handle.net/10453/19598
dc.description.abstract The study of phase locked loops (PLL) has been heavily treated in literature and most of the theoretical and the analytical results of such are verified using simulations. Here we provide a real-time implementation of a PLL on a digital signal processor (DSP) and analyse and verify the theoretical results associated with it on the implemented system. Such work takes us one step above from the traditional simulation and analysis of PLL to real-time implementation and analysis. The steady state and the acquisition of the PLL are analysed. Issues such as quantization errors are also discussed. en_AU
dc.format.extent 329296 bytes
dc.format.mimetype application/pdf
dc.language.iso en_AU
dc.title A Software Phase-Locked Loop from Theory to Practice: TMS320C6000 DSP Based Implementation and Analysis en_AU


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